As integrated circuit devices have become smaller, it is increasingly important to ensure that functional and reliable connections between integrated circuit devices and conductor elements within the integrated circuits can be readily and efficiently achieved and manufactured while maintaining the required miniaturization. In keeping with this requirement, connections in integrated circuits in which Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used, are often made through the use of polycide gate electrodes. Commonly, the polycide gate electrode is a tungsten silicide polycide gate electrode formed of a tungsten silicide upper layer and a polysilicon lower layer which in turn resides upon a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) gate oxide layer.
Although tungsten silicide polycide gate electrodes within Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) provide good surfaces onto which contact with conductor elements can be established, these types of arrangements tend to suffer from various drawbacks. For example, attempts to form layers of tungsten silicide on polysilicon surfaces has resulted in adhesion problems whereby the silicide layer has exhibited a tendency to lift and thus reduce the production efficiency of such arrangements. An additional problem resides in that tungsten silicide polycide gate electrodes also tend to suffer from excess fluorine migration. This fluorine originates from tungsten hexafluoride, which is one of the materials used in chemical vapor deposition (CVD) of the tungsten silicide layer, and tends to occur between the tungsten silicide layer and the polysilicon layer/oxide layer interface therebelow, under high temperature annealing. This results in the thickness of the gate oxide layer having to be increased resulting in an increased stack height.
A further problem which is encountered with this particular type of arrangement resides in that dopants from within the polysilicon layer, tend to redistribute during the thermal processing of the tungsten silicide polycide gate electrode. A yet further problem resides in that the tungsten silicide layers exhibit a high resistivity when formed upon large grain polysilicon layers.
In connection with the above mentioned problems, a method of forming a gate electrode for multiple polysilicon layer has been disclosed in U.S. Pat. No. 5,350,698 issued to Huang et al. This reference discloses the formation of multiple amorphous silicon layers which are each separated by a silicon oxide layer, and which are subsequently annealed to form polysilicon layers. An optional terminal tungsten silicide layer is also disclosed.
This arrangement is directed to limiting the channeling of ion implants which occurs through single polysilicon layers of equivalent thickness. Multiple amorphous silicon layers are discloses as being preferred since as a result of annealing, they form a larger grain size than encountered with equivalent types of multiple polysilicon layer structures.
Another technique proposed in connection with these drawbacks resides in a method wherein the stacked amorphous silicon (SAS) multilayer structures are used without these interleaved silicon oxide layers. This latter type of stacked amorphous silicon (SAS) multilayer structure, when annealed to form the polysilicon layers, is intended to improve the performance of the resulting integrated circuit device. More specifically, the use of stacked amorphous silicon (SAS) multiple layer structures has, following annealing, been used to suppress boron penetration from polysilicon gate electrodes into underlying thin gate oxide layers within P-metal oxide semiconductor field effect transistors (pMOSFETs).
MOSFETs having tungsten silicide polycide gate electrodes which exhibit good diffusion barrier properties, good dopant retention properties, and good contact resistance properties, are disclosed in U.S. Pat. No. 5,710,454 issued to Wu on Jan. 20, 1998. This reference discloses a method of forming tungsten silicide polycide gate electrodes within a metal oxide semiconductor field effect transistor (MOSFET) that is directed to limiting redistribution of dopants from within the polysilicon layer of the tungsten silicide polycide gate electrode.
In accordance with the technique disclosed in Wu, a semiconductor substrate gate oxide layer is firstly formed. A first polysilicon layer is then formed on this gate oxide layer by initially forming an amorphous silicon layer and then annealing this layer in a manner which converts it to polysilicon. Subsequent polysilicon layers are then formed through a similar process. That is to say, further amorphous silicon layers are formed and then converted into polysilicon by way of annealing. A tungsten silicide layer is then formed on the uppermost polysilicon layer through the use of chemical vapor deposition (CVD). With this method, the first and second polysilicon layers have a crystallite size no greater than 0.3 microns, and have a dopant concentration of greater than 1E16 atoms cm.sup.3.
While Wu's method purports to inhibit the diffusion of fluorine from the tungsten silicide layer through the thermal annealing of a stacked amorphous silicon (SAS) multilayer structure, it has nevertheless tended to suffer from the drawback that the tungsten silicide layer tends to separate, that is to say undergo lifting, from the underlying polysilicon layers, with the result that productivity is accordingly reduced.
Accordingly, there exists a need for a stack gate structure which exhibits low resistively, good resistance to layer lifting or separation, and which also permits the height of the stack to be reduced.